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<p>Video Processing Subsystem configuration structure.  
 <a href="struct_x_v___hdmi_rx_ss___config.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a42505911ca30fec2643df7f350e0831e"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#a42505911ca30fec2643df7f350e0831e">DeviceId</a></td></tr>
<tr class="memdesc:a42505911ca30fec2643df7f350e0831e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#a42505911ca30fec2643df7f350e0831e">More...</a><br/></td></tr>
<tr class="separator:a42505911ca30fec2643df7f350e0831e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63cf365a205b7f982be654194c765353"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#a63cf365a205b7f982be654194c765353">BaseAddress</a></td></tr>
<tr class="memdesc:a63cf365a205b7f982be654194c765353"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> BaseAddress is the physical base address of the
</pre><p> subsystem address range  <a href="#a63cf365a205b7f982be654194c765353">More...</a><br/></td></tr>
<tr class="separator:a63cf365a205b7f982be654194c765353"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a562269100fac731d4735038b6fdeb37a"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#a562269100fac731d4735038b6fdeb37a">HighAddress</a></td></tr>
<tr class="memdesc:a562269100fac731d4735038b6fdeb37a"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment"> HighAddress is the physical MAX address of the
</pre><p> subsystem address range  <a href="#a562269100fac731d4735038b6fdeb37a">More...</a><br/></td></tr>
<tr class="separator:a562269100fac731d4735038b6fdeb37a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3bc6c803098c13d8b8d6bce5920c10f"><td class="memItemLeft" align="right" valign="top">XVidC_PixelsPerClock&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#ae3bc6c803098c13d8b8d6bce5920c10f">Ppc</a></td></tr>
<tr class="memdesc:ae3bc6c803098c13d8b8d6bce5920c10f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Supported Pixel per Clock.  <a href="#ae3bc6c803098c13d8b8d6bce5920c10f">More...</a><br/></td></tr>
<tr class="separator:ae3bc6c803098c13d8b8d6bce5920c10f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee79d98ebde06a2f3605a6e3a1566316"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#aee79d98ebde06a2f3605a6e3a1566316">MaxBitsPerPixel</a></td></tr>
<tr class="memdesc:aee79d98ebde06a2f3605a6e3a1566316"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Supported Color Depth.  <a href="#aee79d98ebde06a2f3605a6e3a1566316">More...</a><br/></td></tr>
<tr class="separator:aee79d98ebde06a2f3605a6e3a1566316"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2059d6ab17d86b73b79a6d45928a2dfc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#a2059d6ab17d86b73b79a6d45928a2dfc">HdcpTimer</a></td></tr>
<tr class="memdesc:a2059d6ab17d86b73b79a6d45928a2dfc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a2059d6ab17d86b73b79a6d45928a2dfc">More...</a><br/></td></tr>
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<tr class="memitem:ac2fbb1bb237fb962318fd3e6512abdb2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#ac2fbb1bb237fb962318fd3e6512abdb2">Hdcp14</a></td></tr>
<tr class="memdesc:ac2fbb1bb237fb962318fd3e6512abdb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ac2fbb1bb237fb962318fd3e6512abdb2">More...</a><br/></td></tr>
<tr class="separator:ac2fbb1bb237fb962318fd3e6512abdb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c83dac27c643fce4f90a5a082c1f3d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#a5c83dac27c643fce4f90a5a082c1f3d8">Hdcp22</a></td></tr>
<tr class="memdesc:a5c83dac27c643fce4f90a5a082c1f3d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a5c83dac27c643fce4f90a5a082c1f3d8">More...</a><br/></td></tr>
<tr class="separator:a5c83dac27c643fce4f90a5a082c1f3d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad08f9bc0025dc447f1d91d62e03d6c89"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_rx_ss___config.html#ad08f9bc0025dc447f1d91d62e03d6c89">HdmiRx</a></td></tr>
<tr class="memdesc:ad08f9bc0025dc447f1d91d62e03d6c89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ad08f9bc0025dc447f1d91d62e03d6c89">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Video Processing Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a63cf365a205b7f982be654194c765353"></a>
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          <td class="memname">UINTPTR XV_HdmiRxSs_Config::BaseAddress</td>
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<p><pre class="fragment"> BaseAddress is the physical base address of the
</pre><p> subsystem address range </p>

<p>Referenced by <a class="el" href="xv__hdmirxss_8h.html#aaf2419b376d0b737a59d86da1ef67bcf">XV_HdmiRxSs_CfgInitialize()</a>, and <a class="el" href="group__v__hdmirxss.html#gabddcd7be105900eea60e7c51158ae22d">XV_HdmiRxSs_SubcoreInitHdmiRx()</a>.</p>

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          <td class="memname">u16 XV_HdmiRxSs_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss_8h.html#aaf2419b376d0b737a59d86da1ef67bcf">XV_HdmiRxSs_CfgInitialize()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a> XV_HdmiRxSs_Config::Hdcp14</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a> XV_HdmiRxSs_Config::Hdcp22</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a> XV_HdmiRxSs_Config::HdcpTimer</td>
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<p>Sub-core instance configuration. </p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_rx_ss___sub_core.html">XV_HdmiRxSs_SubCore</a> XV_HdmiRxSs_Config::HdmiRx</td>
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<p>Sub-core instance configuration. </p>

<p>Referenced by <a class="el" href="group__v__hdmirxss.html#gabddcd7be105900eea60e7c51158ae22d">XV_HdmiRxSs_SubcoreInitHdmiRx()</a>.</p>

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<p><pre class="fragment"> HighAddress is the physical MAX address of the
</pre><p> subsystem address range </p>

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          <td class="memname">u8 XV_HdmiRxSs_Config::MaxBitsPerPixel</td>
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<p>Maximum Supported Color Depth. </p>

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          <td class="memname">XVidC_PixelsPerClock XV_HdmiRxSs_Config::Ppc</td>
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<p>Supported Pixel per Clock. </p>

<p>Referenced by <a class="el" href="xv__hdmirxss_8h.html#a93b6769e137d23ae6a4fe0d61864f5cd">XV_HdmiRxSs_SetDefaultPpc()</a>, <a class="el" href="xv__hdmirxss_8h.html#a7296f98d74b618438a08c0bb4d303350">XV_HdmiRxSs_SetPpc()</a>, and <a class="el" href="xv__hdmirxss_8h.html#a6156f804fb138799bb3bd9a243dd36cf">XV_HdmiRxSs_SetStream()</a>.</p>

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